Aug 5, 2022 · Hello, I am trying to connect AXI stream interconnect module to another module (which is a verilog file). I am adding the interconnect ...

I am using external SOF through TUSER(0). Data is passed from logic to VDMA core through a own IP which controls all AXI 4 Stream signals required. Data is sent ...

Jan 10, 2019 · The output stage of my core is made using a FWFT FIFO with VALID and EMPTY signal and is mapped to the AXIS_M in the following way :.

Jul 14, 2022 · I try to use the Broadcaster IP (Vivado 2021.2) to split a wide 256-bit stream into 4 equal parallel streams (in connection with this ...

Oct 12, 2019 · Hello, I'm debugging an issue on the Xilinx ZCU102 board where I've configured an external camera sensor and the MIPI CSI-2 RX subsystem to ...

Jun 28, 2023 · Synthesis completes without errors, but I get the following errors during implementation: [DRC RTSTAT-2] Partially routed nets: 7 net(s) are ...