Sep 22, 2017 · Hi everyone, I have a problem with my design on Zynq7. Not really a problem, an incomprehension. The PS part uses a clock (ps_clk) at 40MHz, ...

Jul 15, 2020 · Hello, I have i design with multiple clock domains. I have my custom IP (clkx1) clock , and would like to interconnect it with PS via an AXI ...

Aug 2, 2013 · I've currently got a design that's mostly working using the AXI_INTERCONNECT block. All ports to/from are 64 bits or less. The max clock rate is ...

Sep 6, 2019 · We are now encountering a timing issue within one of the Smart Interconnects we've incorporated on a 100 MHz clock domain. Seeing this ...

Mar 28, 2020 · Hi all, I have a 2 to 1 AXI interconnect with two masters sharing access to one slave memory controller interface.

Aug 16, 2019 · Hi everbody, I have hopefully a very simple issue, but dont find a way to fix it. The AXI interconnect is missing internal clock and reset ...

Hi I'm using AXI Interconnect to do both data width and clock conversion. My DDR3 is driven with a 200MHz clock at a 128 bitwidth, while my custom VHDL code ...